Systems and Methods for a Data Processing Using Integrated Filter Circuit

ABSTRACT

Systems and methods are disclosed relating generally to data processing, and more particularly to applying low pass and rotation filtering in relation to data processing. For example, a system may include a phase modification value determination circuit operable to generate a phase offset value based upon an input data set derived from information sensed from a storage medium. The system may include an integrated low pass and rotation filtering circuit operable to simultaneously apply a low pass filtering function and phase rotation function to a series of digital samples derived from the information sensed from the storage medium to yield a modified output. Application of both the low pass filtering and phase rotation functions is governed at least in part based upon a selected coefficient set corresponding to a combination of the phase off set value and a boost value.

FIELD OF THE INVENTION

Systems and methods relating generally to data processing, and more particularly to applying low pass and rotation filtering in relation to data processing.

BACKGROUND

Processing a data set from a storage medium typically involves performing a timing acquisition process to synchronize to a received data set. When the timing is finally acquired, one or more data parameters may be modified using the data received after the timing synchronization is complete. Such an approach works well in some scenarios, but may result in increased overhead in other scenarios.

Hence, for at least the aforementioned reasons, there exists a need in the art for advanced systems and methods for accessing data from a storage medium.

SUMMARY

Systems and methods relating generally to data processing, and more particularly to applying low pass and rotation filtering in relation to data processing.

This summary provides only a general outline of some embodiments of the invention. The phrases “in one embodiment,” “according to one embodiment,” “in various embodiments”, “in one or more embodiments”, “in particular embodiments” and the like generally mean the particular feature, structure, or characteristic following the phrase is included in at least one embodiment of the present invention, and may be included in more than one embodiment of the present invention. Importantly, such phases do not necessarily refer to the same embodiment. Many other embodiments of the invention will become more fully apparent from the following detailed description, the appended claims and the accompanying drawings.

BRIEF DESCRIPTION OF THE FIGURES

A further understanding of the various embodiments of the present invention may be realized by reference to the figures which are described in remaining portions of the specification. In the figures, like reference numerals are used throughout several figures to refer to similar components. In some instances, a sub-label consisting of a lower case letter is associated with a reference numeral to denote one of multiple similar components. When reference is made to a reference numeral without specification to an existing sub-label, it is intended to refer to all such multiple similar components.

FIG. 1 is a block diagram of a storage medium and sector data schemes that may be used with a data processing system in accordance with one or more embodiments of the present invention;

FIG. 2 shows a storage system that includes integrated low pass and rotation filtering circuitry in accordance with various embodiments of the present invention;

FIG. 3 is a block diagram of a data processing circuit including integrated low pass and rotation filtering circuitry in accordance with some embodiments of the present invention;

FIG. 4 is a flow diagram showing a method in accordance with some embodiments of the present invention for integrated low pass and rotation filtering;

FIG. 5 is a flow diagram showing a method for acquisition phase gain modification; and

FIG. 6 is a block diagram of another data processing circuit including integrated low pass and rotation filtering circuitry in accordance with various embodiments of the present invention.

DETAILED DESCRIPTION OF SOME EMBODIMENTS

Systems and methods relating generally to data processing, and more particularly to applying low pass and rotation filtering in relation to data processing.

Some embodiments provide data processing systems that include a phase modification value determination circuit and an integrated low pass and rotation filtering circuit. The phase modification value determination circuit is operable to generate a phase offset value based upon an input data set derived from information sensed from a storage medium. The integrated low pass and rotation filtering circuit is operable to simultaneously apply a low pass filtering function and phase rotation functions to a series of digital samples derived from the information sensed from the storage medium to yield a modified output. Application of both the low pass filtering and phase rotation functions is governed at least in part based upon a selected coefficient set corresponding to a combination of the phase offset value and a boost value. In some cases, boost value is user programmable.

In various instances of the aforementioned embodiments, the low pass and rotation filtering circuit includes a look up table operable to maintain a plurality of coefficient sets including the selected coefficient set, and an integrated low pass and interpolation filter circuit operable to simultaneously apply the low pass filtering and phase rotation functions to the series of digital samples. In some such instances, a boost and phase adjustment selection circuit is included. The boost and phase adjustment selection circuit is operable to determine a look up value corresponding to the selected coefficient set based upon the combination of the phase offset value and the boost value. In some cases, the coefficient set includes at least two bits, and at least one of the at least two bits when modified impacts both the low pass filtering function and the phase rotation function. In various cases, the coefficient set includes at least two bits, and all of the at least two bits when modified each impact both the low pass filtering function and the phase rotation function.

In some instances of the aforementioned embodiments, the phase modification value determination circuit includes a first circuit and a second circuit. The first circuit is operable to generate a first value during an acquisition mode and the second circuit is operable to generate a second value during a tracking mode. The first value is selected as the phase offset value during the acquisition mode, and the second value is selected as the phase offset value during the tracking mode.

In particular instances of the aforementioned embodiments, the systems are implemented as part of a storage device. The storage device includes: the storage medium; a head disposed in relation to the storage medium, and operable to sense the information from the storage medium; and an analog to digital converter circuit operable to convert an input derived from the information set into the series of digital samples. In particular cases, the systems further include: an equalizer circuit operable to equalize the modified output to yield an equalized output; a data detector circuit operating on the equalized output to yield a detected output; and a timing update loop circuit operable to generate the phase offset value.

Other embodiments of the present invention provide methods for integrated filtering and phase rotation that includes: receiving a series of digital samples; determining a phase offset value based upon the series of digital samples; and using an integrated low pass and rotation filtering circuit to simultaneously apply a low pass filtering function and phase rotation function to the series of digital samples to yield a modified output. Application of both the low pass filtering and phase rotation functions is governed at least in part based upon a selected coefficient set corresponding to a combination of the phase offset value and a boost value. In some cases, boost value is user programmable.

In some instances of the aforementioned embodiments, applying the low pass function and rotation filtering function includes accessing a look up table programmed to include a plurality of coefficient sets. The selected coefficient set is one of the plurality of coefficient sets. In some cases, applying the low pass function and rotation filtering function includes determining a look up value corresponding to the selected coefficient set based upon the combination of the phase offset value and the boost value. In one particular case, determining the look up value includes concatenating the boost value and the phase offset value.

Turning to FIG. 1, a storage medium 1 is shown with two exemplary tracks 20, 22 that are adjacent to one another and indicated as dashed lines. The tracks are divided into sectors by servo data written within wedges 19, 18. These wedges include servo data 10 that are used for control and synchronization of a read/write head assembly over a desired location on storage medium 1. In particular, this servo data generally includes a preamble pattern 11 followed by a sector address mark 12 (SAM). Sector address mark 12 may include wedge identification information followed by the SAM. Sector address mark 12 is followed by a Gray code 13, and Gray code 13 is followed by burst information 14. Gray code 13 may include track identification information. It should be noted that while two tracks and two wedges are shown, hundreds of each would typically be included on a given storage medium. Further, it should be noted that a servo data set may have two or more fields of burst information. Yet further, it should be noted that different information may be included in the servo fields such as, for example, repeatable run-out information that may appear after burst information 14.

Between the servo data bit patterns 10 a and 10 b, a user data region 16 is provided. User data region 16 includes some synchronization and header data 90 that includes a preamble pattern 91 and a head data 92 followed by user data within user data region 16. Based upon the disclosure provided herein, one of ordinary skill in the art will recognize a variety of data that may be included in header data 92.

In operation, storage medium 1 is rotated in relation to a sensor that senses information from the storage medium. In a read operation, the sensor would sense servo data from wedge 19 (i.e., during a servo data period) followed by user data from a user data region between wedge 19 and wedge 18 (i.e., during a user data period) and then servo data from wedge 18. When reading data in user data region 16, synchronization to the data is done through use of preamble 91. In a write operation, the sensor would sense servo data from wedge 19 then write data to the user data region between wedge 19 and wedge 18. Then, the sensor would be switched to sense a remaining portion of the user data region followed by the servo data from wedge 18. Of note, wedges 18, 19 follow arcs corresponding to the geometry of an arm and pivot as is known in the art.

Codewords may be stored to the tracks on storage medium 1 in two different formats. In a parallel format 30, a given codeword is distributed across two tracks (e.g., tracks 20, 22). Parallel format 30 includes writing a first portion (e.g., CW1.A1 31) of a codeword to a first track and a second portion (e.g., CW1.A2 32) of the same codeword to a second track adjacent to the first track. This is followed by first portions of other codewords (e.g., CW2.B1 33, CWN.X1 35) stored serially along the first track, and second portions of other codewords (e.g., CW2.B2 34, CWN.X2 36) stored serially along the second track. The portions along the first track may be co-positioned with the portions along the second track such that portions for the same codeword can be read in parallel with one sensor of the head being disposed over one track and another sensor of the head disposed over the second track. Such parallel distribution of codeword portions allow for accessing a given codeword using multiple heads at a greater rate than if the codewords were accessed from a single track. In a serial format 40, codewords (e.g., CW1 41, CW2 42 and CWN 43) are placed in serial fashion along one track.

Turning to FIG. 2, a storage system 200 is shown that includes a read channel 210 having integrated low pass and rotation filtering circuitry in accordance with one or more embodiments of the present invention. In addition to read channel 210, storage system 200 includes a read/write head 276, a preamplifier circuit 270, an interface controller 220, a hard disk controller 266, a motor controller 268, a spindle motor 272, and a disk platter 278. Storage system 200 may be, for example, a hard disk drive. Read/write head 276 includes one or more read heads distributed at different locations along the read/write head, and at least one write head. Interface controller 220 controls addressing and timing of data to/from disk platter 278, and interacts with a host controller (not shown). The data on disk platter 278 consists of groups of magnetic signals that may be detected by read/write head assembly 276 when the assembly is properly positioned over disk platter 278. In one embodiment, disk platter 278 includes magnetic signals recorded in accordance with either a longitudinal or a perpendicular recording scheme.

In a typical read operation, read/write head 276 is accurately positioned by motor controller 268 over a desired data track on disk platter 278. Motor controller 268 both positions read/write head 276 in relation to disk platter 278 and drives spindle motor 272 by moving read/write head assembly 276 to the proper data track on disk platter 278 under the direction of hard disk controller 266. Spindle motor 272 spins disk platter 278 at a determined spin rate (RPMs). Once read/write head 276 is positioned adjacent the proper data track, magnetic signals representing data on disk platter 278 are sensed by each of the sensors included in three sensor read/write head 276 as disk platter 278 is rotated by spindle motor 272. The sensed magnetic signals are provided as a continuous, minute analog signal representative of the magnetic data on disk platter 278 with a signal stream being provided from each read head. These one or more minute analog signals are transferred from read/write head 276 to read channel circuit 210 via preamplifier 270. Preamplifier 270 is operable to amplify the individual minute analog signals accessed from disk platter 278. In turn, read channel circuit 210 processes the amplified signal(s) including combining the signals where two or more read heads are used and applying data decoding to the single or combined signals to recreate the information originally written to disk platter 278. This data is provided as read data 203 to a receiving circuit. A write operation is substantially the opposite of the preceding read operation with write data 201 being provided to read channel circuit 210. This data is then encoded and written to disk platter 278.

As part of processing data derived from the one or more read heads included in read/write head 276, an acquisition phase is traversed during which timing and phase alignment with data received from disk platter 278 is performed. Once the timing and phase alignment is achieved, standard processing of the data retrieved from disk platter 278 is performed during a tracking phase. Gain parameters used to control a variable gain amplifier included as part of read channel 210 are modified both in the acquisition phase and in the tracking phase. During both gain and tracking phases, a combination of low pass filtering and rotation filtering is applied. This combination of low pass filtering and rotation filtering is done using integrated low pass and rotation filtering circuitry where a unified circuit applies the combination of low pass filtering and rotation filtering simultaneously based upon a unified parameter set where at least one element of the unified parameter set affects both the low pass filtering and the rotation filtering. The combination of low pass filtering and rotation filtering may be done using an integrated low pass and rotation filter circuit similar to that discussed below in relation to FIG. 3, and/or may be performed using the method discussed below in relation to FIG. 4.

It should be noted that storage system 200 may be integrated into a larger storage system such as, for example, a RAID (redundant array of inexpensive disks or redundant array of independent disks) based storage system. Such a RAID storage system increases stability and reliability through redundancy, combining multiple disks as a logical unit. Data may be spread across a number of disks included in the RAID storage system according to a variety of algorithms and accessed by an operating system as if it were a single disk. For example, data may be mirrored to multiple disks in the RAID storage system, or may be sliced and distributed across multiple disks in a number of techniques. If a small number of disks in the RAID storage system fail or become unavailable, error correction techniques may be used to recreate the missing data based on the remaining portions of the data from the other disks in the RAID storage system. The disks in the RAID storage system may be, but are not limited to, individual storage systems such as storage system 200, and may be located in close proximity to each other or distributed more widely for increased security. In a write operation, write data is provided to a controller, which stores the write data across the disks, for example by mirroring or by striping the write data. In a read operation, the controller retrieves the data from the disks. The controller then yields the resulting read data as if the RAID storage system were a single disk.

A data decoder circuit used in relation to read channel circuit 210 may be, but is not limited to, a low density parity check (LDPC) decoder circuit as are known in the art. Such low density parity check technology is applicable to transmission of information over virtually any channel or storage of information on virtually any media. Transmission applications include, but are not limited to, optical fiber, radio frequency channels, wired or wireless local area networks, digital subscriber line technologies, wireless cellular, Ethernet over any medium such as copper or optical fiber, cable channels such as cable television, and Earth-satellite communications. Storage applications include, but are not limited to, hard disk drives, compact disks, digital video disks, magnetic tapes and memory devices such as DRAM, NAND flash, NOR flash, other non-volatile memories and solid state drives.

In addition, it should be noted that storage system 200 may be modified to include solid state memory that is used to store data in addition to the storage offered by disk platter 278. This solid state memory may be used in parallel to disk platter 278 to provide additional storage. In such a case, the solid state memory receives and provides information directly to read channel circuit 210. Alternatively, the solid state memory may be used as a cache where it offers faster access time than that offered by disk platted 278. In such a case, the solid state memory may be disposed between interface controller 220 and read channel circuit 210 where it operates as a pass through to disk platter 278 when requested data is not available in the solid state memory or when the solid state memory does not have sufficient storage to hold a newly written data set. Based upon the disclosure provided herein, one of ordinary skill in the art will recognize a variety of storage systems including both disk platter 278 and a solid state memory.

Turning to FIG. 3, a block diagram of a data processing circuit 300 including an integrated low pass and rotation filtering circuit 319 in accordance with some embodiments of the present invention. Data processing circuit 300 includes a preamplifier circuit 304 that receives data 302 from a read head included as part of a read/write head (not shown). Data 302 is received as an analog signal derived from sensing information from a track on the storage medium (not shown). Preamplifier circuit 304 amplifies data 302 to yield an amplified signal 306 that is provided to a variable gain amplifier circuit 307 that amplifies amplified signal 306 in accordance with an acquisition gain feedback value 384 or a non-acquisition gain feedback value 336 to yield a variably amplified output that is provided to an analog to digital converter circuit 308. Analog to digital converter circuit 308 converts the aforementioned variably amplified output to yield a series of corresponding digital samples 310. Based upon the disclosure provided herein, one of ordinary skill in the art will recognize various analog to digital conversion circuits that may be used in relation to different embodiments of the present invention. Of note, other circuitry may be included in addition to variable gain amplifier circuit 307 and analog to digital converter circuit 308 as part of overall analog front end processing circuitry. Such other circuitry may include, but is not limited to, an analog filter, DC offset (not shown), and magneto resistive asymmetry (MRA) modification circuitry (not shown). Based upon the disclosure provided herein, one of ordinary skill in the art will recognize a variety of circuitry in addition to variable gain amplifier circuit 307 and analog to digital converter circuit 308 that may be included as part of overall analog front end circuitry.

Digital samples 310 are provided to a first in/first out buffer circuit 312 where digital samples 310 are stored as buffered samples 332. Buffered samples 332 are provided to integrated low pass and rotation filtering circuit 319 where they are simultaneously low pass filtered and phase rotated to yield modified samples 318. The simultaneous low pass filtering and phase rotation is controlled by a combination of either: a phase adjustment 325 and a user programmable filter boost 303 during acquisition phase processing mode (i.e., the processing of header data associated with a user data set); or a loop timing feedback 326 and user programmable filter boost 303 during tracking phase processing mode (i.e., the processing of user data in the data set that follows the header data).

Integrated low pass and rotation filtering circuit 319 includes a boost and phase adjustment selection circuit 311, a look up table 315, and an integrated digital low pass and interpolation filter circuit 316. In operation, integrated digital low pass and interpolation filter circuit 316 simultaneously applies both a low pass filtering function and a phase rotation function to buffer samples 332 to yield modified samples 318 based upon a coefficient set 317 from look up table 315. In some cases, coefficient set 317 includes two or more bits where at least one of the two or more bits when modified impacts both the low pass filtering function and the phase rotation function. In other cases, coefficient set 317 includes two or more bits where all of the two or more bits when modified each impact both the low pass filtering function and the phase rotation function. As more fully described below, coefficient set 317 is generated based upon a combination of a phase offset value and a boost value.

The offset value is either phase adjustment 325 or loop timing feedback 326 depending upon whether circuit 300 is operating in acquisition mode or in tracking mode. The phase offset value is calculated by a phase modification value determination circuit. In some cases, the phase modification value determination circuit is a single circuit that operates the same regardless of the mode of operation in which data processing circuit 300 is operating. In other cases, the phase modification value determination circuit operates differently in an acquisition mode than in a tracking mode. In some particular cases, the phase modification value determination circuit includes one set of circuitry to adjust a phase value in the acquisition mode and another set of circuitry to adjust the phase value in the tracking mode. As shown, data processing circuit 300 includes: circuitry to adjust a phase value in the acquisition mode (including, but not limited to, a phase/frequency detection circuit 324), and circuitry to adjust the phase value in the tracking mode (including, but not limited to, a timing update loop circuit 390).

Boost and phase selection circuit 311 receives phase offset values (i.e., phase adjustment 325 and loop timing feedback 326) and user programmable filter boost value 303. During the tracking phase processing mode, boost and phase selection circuit 311 determines a look up value 313 based upon a combination of timing loop feedback 326. Alternatively, during the acquisition phase processing mode, boost and phase selection circuit 311 determines a look up value 313 based upon a combination of phase adjustment 325. In either of the acquisition phase processing mode or the tracking phase processing mode, the determination of look up value 313 by boost and phase selection circuit 311 is the same. In some embodiments of the present invention, boost and phase selection circuit 311 determines look up value 313 by concatenating boost value 303 to the relevant phase offset value (i.e., either phase adjustment 325 or loop timing feedback 326 depending upon whether the acquisition or tracking mode processing is ongoing). Alternatively, boost and phase selection circuit 311 determines look up value 313 by applying a combining algorithm to a combination of boost value 303 and the relevant phase offset value (i.e., either phase adjustment 325 or loop timing feedback 326 depending upon whether the acquisition or tracking mode processing is ongoing). Based upon the disclosure provided herein, one of ordinary skill in the art will recognize a variety of approaches that may be used to combine the boost value and the phase offset value into a single look up value.

Look up value 313 is provided to look up table 315 that is pre-programmed with a number of coefficient sets each corresponding to different combinations of phase offset and boost to be implemented by integrated digital low pass and interpolation filter circuit 316. In response to receiving look up value 313, look up table 315 provides the corresponding pre-programmed coefficient set as coefficient set 317 to integrated digital low pass and interpolation filter circuit 316.

As more fully discussed below, phase adjustment 325 is calculated to align the received data with a better sample point which makes the retrieved data more easily discerned by a downstream data decoder circuit. The data used to calculate the phase adjustment generated differently depending upon whether the processing is in acquisition phase processing mode (i.e., the processing of header data associated with a user data set) or tracking phase processing mode (i.e., the processing of user data in the data set that follows the header data).

Modified samples 318 are provided to a non-acquisition gain loop circuit 334 that calculates non-acquisition gain feedback value 336. Non-acquisition gain feedback value 336 is used during tracking phase processing by variable gain amplifier circuit 307. Acquisition gain feedback value 384 is not used by variable gain amplifier circuit 307 during tracking phase processing. Non-acquisition gain loop circuit 334 may be any circuit known in the art for generating a gain feedback value using interpolated samples generated during tracking phase processing.

Modified samples 318 are provided to a loop digital finite impulse response filter circuit 320 that equalizes interpolated data 318 to yield an equalized output 329. Equalized output 329 is provided to a loop soft output Viterbi algorithm (SOVA) circuit 392 that applies a SOVA algorithm to yield a decision output 394. Decision output 394 is provided to timing update loop circuit 390 that modifies loop timing feedback 326. In contrast to phase/frequency detection circuit 324 that operates to modify phase during acquisition mode, timing update loop 390 operates to adjust phase during tracking phase processing.

Digital samples 310 and buffered samples 332 are provided to acquisition phase gain modification circuit 362. Acquisition phase gain modification circuit 362 includes an amplitude estimation circuit 364. Amplitude estimation circuit 364 estimates an amplitude of digital samples 310 and provides the estimate as an estimated amplitude output 366. The amplitude estimation may be done, for example, using a zero gain start (ZGS) circuit as are known in the art. Based upon the disclosure provided herein, one of ordinary skill in the art will recognize other approaches and/or circuitry that may be used to estimate the amplitude of digital samples 310.

Estimated amplitude output 366 is provided to a comparator circuit 368 and a comparator circuit 372. Comparator circuit 368 compares estimated amplitude output 366 with a wide window threshold 376 to yield a wide comparison output 370, and comparator circuit 372 compares estimated amplitude output 366 with a narrow window threshold 378 to yield a narrow comparison output 374. In some embodiments, wide window threshold 376 represents a first window around an expected amplitude and includes an upper threshold which is an expected amplitude plus a wide offset and a lower threshold which is the expected amplitude minus the wide offset. The expected amplitude and/or the wide offset may be user programmable. Similarly, narrow window threshold 378 represents a second window around the expected amplitude and includes an upper threshold which is an expected amplitude plus a narrow offset and a lower threshold which is the expected amplitude minus the narrow offset. Where the narrow offset is less than the wide offset, the narrow window is within the wide window. The narrow offset may be user programmable. Narrow comparison output 374 is asserted whenever estimated amplitude output 366 is within a narrow window (i.e., the expected amplitude+/−narrow offset), and wide comparison output 370 is asserted whenever estimated amplitude output 366 is within a wide window (i.e., the expected amplitude+/−wide offset). In a case where the narrow offset is less than the wide offset, then whenever narrow comparison output 374 is asserted, wide comparison output 370 is also asserted. When wide comparison output 370 is asserted and narrow comparison output 374 is not asserted, then estimated amplitude output 366 is outside of the narrow window and within the wide window. When neither wide comparison output 370 not narrow comparison output 374 are asserted, then estimated amplitude output 366 is outside of the wide window.

Wide comparison output 370 and narrow comparison output 374 are provided to an acquisition gain feedback calculation circuit 380. When narrow comparison output 374 is asserted, estimated amplitude output 366 is near the expected amplitude and acquisition gain feedback calculation circuit 380 provides a default gain value as acquisition gain feedback value 384 (i.e., acquisition gain feedback calculation circuit 380 does not modify the gain applied by variable gain amplifier circuit 307). In addition, acquisition gain feedback calculation circuit 380 sets a buffered sample scalar value 385 to unity (i.e., ‘1’).

Alternatively, when narrow comparison output 374 is not asserted and wide comparison output 370 is asserted, estimated amplitude output 366 is an intermediate distance from the expected amplitude. In such a situation, acquisition gain feedback calculation circuit 380 calculates an overall gain offset. The overall gain offset is the magnitude and direction that the gain applied by variable gain amplifier circuit 307 would have to be adjusted to increase or decrease digital samples 310 to match the expected amplitude. Acquisition gain feedback calculation circuit 380 sets a buffered sample scalar value 385 to a positive value (greater than unity) where estimated amplitude output 366 is less than the expected amplitude minus the narrow offset, or sets buffered sample scalar value 385 to a negative value (less than unity) where estimated amplitude output 366 is greater than the expected amplitude plus the narrow offset. The magnitude of buffered sample scalar value 385 corresponds to the calculated overall gain offset. In addition, acquisition gain feedback calculation circuit 380 provides a default gain value as acquisition gain feedback value 384 (i.e., acquisition gain feedback calculation circuit 380 does not modify the gain applied by variable gain amplifier circuit 307).

As yet another alternative, when wide comparison output 370 is not asserted, estimated amplitude output 366 is an extended distance from the expected amplitude. In such a situation, acquisition gain feedback calculation circuit 380 calculates an overall gain offset and a period gain. The overall gain offset is the magnitude and direction that the gain applied by variable gain amplifier circuit 307 would have to be adjusted to increase or decrease digital samples 310 to match the expected amplitude. The period gain is the overall gain divided by a number of bit periods over which the gain will be modified to achieve the overall gain. The number of bit periods are the number of periods (or less than the number of periods) remaining in the region over which the acquisition phase processing is performed. In some embodiments, this number of periods is fixed, while in other embodiments this number of periods is user programmable.

Acquisition gain feedback calculation circuit 380 sets buffered sample scalar value 385 to a positive value (greater than unity) corresponding to the period gain where estimated amplitude output 366 is less than the expected amplitude minus the narrow offset, or sets buffered sample scalar value 385 to a negative value (less than unity) corresponding to the period gain where estimated amplitude output 366 is greater than the expected amplitude plus the narrow offset. In addition, acquisition gain feedback calculation circuit 380 increments acquisition gain feedback value 384 from the default value on a period by period basis by an offset corresponding to the period gain until the overall gain is achieved. By incrementally introducing changes to acquisition gain feedback value 384 rather than instantaneously introducing the overall gain, operational instability due to parameter change is reduced.

Buffered samples 332 are provided to an acquisition feedback correction circuit 386 that multiplies buffered samples 332 by buffered sample scalar value 385 to yield scaled samples 389. Where narrow comparison output 374 is asserted, scaled samples 389 are the same as buffered samples 332 (i.e., buffered sample scalar value 385 is set to unity). Alternatively, where narrow comparison output 374 is not asserted, scaled samples 389 are a scaled version of buffered samples 332 (i.e., buffered sample scalar value 385 is greater than or less than unity). Scaled samples 389 are provided to phase/frequency detection circuit 324. Upon receiving a complete preamble for a given user data set (e.g., preamble 91 of FIG. 1), phase frequency detection circuit 324 calculates phase adjustment 325 which is to be applied to all user data maintained in the memory buffer of filter and buffer circuit 312 by a digital interpolation filter 316. Phase adjustment 325 is calculated to align the received data with a better sample point which makes the retrieved data more easily discerned by a downstream data decoder circuit. The phase adjustment is calculated differently depending upon whether the processing is in acquisition mode (i.e., the processing of header data associated with a user data set) or tracking mode (i.e., the processing of user data in the data set that follows the header data). Phase frequency detection circuit 324 may be implemented as any circuit known in the art to detect a phase/frequency offset. Based upon the disclosure provided herein, one of ordinary skill in the art will recognize a variety of circuits that may be used to perform the function of phase frequency detection circuit 324.

During tracking phase processing, gain adjustment is performed consistent with other circuits known in the art. As discussed above, data processing circuit 300 additionally performs gain adjustment during acquisition phase processing. Such gain adjustment during acquisition phase processing includes variable gain amplifier circuit 307 amplifying amplified signal 306 by a variable gain controlled by acquisition gain feedback value 384 to yield variably amplified output (non-acquisition gain feedback value 336 is not used during acquisition phase processing). Analog to digital converter circuit 308 converts the variably amplified output into a corresponding series of digital samples 310. Digital samples 310 are stored to FIFO buffer 312.

The amplitude of digital samples 310 is estimated by amplitude estimation circuit 364 to yield estimated amplitude 366. Based upon wide comparison output 370 and narrow comparison output 374, gain feedback calculation circuit 380 determines whether estimated amplitude 366 is within a narrow window defined by narrow window threshold 378 and/or a wide window defined by wide threshold 376. Where gain feedback calculation circuit 380 determines that estimated amplitude 366 is within the narrow window, estimated amplitude 366 is near the expected amplitude, and gain feedback calculation circuit sets buffered sample scalar value 385 to unity and leaves acquisition gain feedback value 384 unchanged. Alternatively, where gain feedback calculation circuit 380 determines that estimated amplitude 366 is not within the narrow window, gain feedback calculation circuit 380 calculates the overall gain offset. The process of modifying the gain continues only during the acquisition phase processing. Once the tracking phase processing begins, gain feedback calculation circuit 380 sets buffered sample scalar value 385 to unity, and variable gain amplifier 307 uses non-acquisition gain feedback value 336 to guide application of the variable gain and ignores acquisition gain feedback value 384.

Where gain feedback calculation circuit 380 additionally determines that estimated amplitude 366 is within the wide window, estimated amplitude 366 is an intermediate distance from the expected amplitude. In such a case, gain feedback calculation circuit 380 leaves acquisition gain feedback value 384 unchanged and modifies buffered sample scalar value 385 to compensate for the overall gain offset. In particular, where the overall gain offset is positive indicating a need for increasing the gain applied by the variable gain amplification process, gain feedback calculation circuit 380 sets buffered sample scalar value 385 to greater than unity by an amount corresponding to the magnitude of the overall gain offset. Otherwise, where the overall gain offset is negative indicating a need for decreasing the gain applied by the variable gain amplification process, gain feedback calculation circuit 380 sets buffered sample scalar value 385 to less than unity by an amount corresponding to the magnitude of the overall gain offset. Said another way, the gain being applied by variable gain amplifier circuit 307 is not changed, but buffered samples 332 are scaled by acquisition feedback circuit 386 by an amount indicated by buffered sample scalar value 385. The process of modifying the gain continues until the tracking phase processing begins. Once the tracking phase processing begins, gain feedback calculation circuit 380 sets buffered sample scalar value 385 to unity, and variable gain amplifier 307 uses non-acquisition gain feedback value 336 to guide application of the variable gain and ignores acquisition gain feedback value 384.

Alternatively, where gain feedback calculation circuit 380 additionally determines that estimated amplitude 366 is not within the wide window, estimated amplitude 366 is an extended distance from the expected amplitude. In such a case, gain feedback calculation circuit 380 divides the previously calculated overall gain offset by a number of bit periods over which the gain will be modified to achieve the overall gain. This division yields a period gain. Gain feedback calculation circuit 380 incrementally modifies buffered sample scalar value 385 to reflect the period gain. This incremental application includes setting buffered sample scalar value 385 to correspond to the period gain for a first bit period, and increasing buffered sample scalar value 385 by the period gain for each subsequent bit period. Thus, during the second bit period buffered sample scalar value 385 reflects two times the period gain, during the third bit period buffered sample scalar value 385 reflects three times the period gain, and so on. In addition, gain feedback calculation circuit 380 incrementally modifies acquisition gain feedback value 384 to reflect the period gain. This incremental modification of acquisition gain feedback value 384 includes modifying acquisition gain feedback value 384 to introduce a change corresponding to the period gain for a first bit period, and increasing (or decreasing) the gain feedback by an amount corresponding to the period gain for each subsequent bit period. Thus, during the second bit period the gain feedback is modified to reflect two times the period gain, during the third bit period the gain feedback is modified to reflect three times the period gain, and so on. The process of modifying the gain continues until the overall gain offset is achieved by incrementally applying the period gain or until the tracking phase processing begins. Once the tracking phase processing begins, gain feedback calculation circuit 380 sets buffered sample scalar value 385 to unity, and variable gain amplifier 307 uses non-acquisition gain feedback value 336 to guide application of the variable gain and ignores acquisition gain feedback value 384.

Turning to FIG. 4, a flow diagram 400 shows a method in accordance with some embodiments of the present invention for integrated low pass and rotation filtering. Following flow diagram 400, a user programmable boost value is received (block 405). This boost value is a user selectable setting indicating an amount of boost (or db gain) that is to be applied to digital samples derived from a storage medium. This may be received from a register holding the user programmable value, and writable via a user interface. Based upon the disclosure provided herein, one of ordinary skill in the art will recognize a variety of approaches that may be used to provide the user programmable boost value.

Data is received from a sensor (block 410). The sensor may be a read head flying over the surface of a storage medium. In such a case, the data is derived from information stored on the storage medium. The data is amplified to yield an amplified output (block 415). The data is in the form of an analog signal, and the amplification is done using an analog signal amplifier circuit. In some cases, the analog signal amplifier circuit is a preamplifier circuit as are known in the art. Various analog processing is applied to the amplified output to yield digital samples (block 420). Such analog processing may include, but is not limited to, variable gain amplification, analog filtering, and/or analog to digital conversion.

A combination of low pass and digital interpolation filtering are simultaneously applied to the digital samples to yield a filtered output (block 425). The combination of the low pass and digital interpolation filtering is based upon a coefficient set including two or more bits. The coefficient set controls the simultaneous low pass and interpolation. In some cases all of the two or more bits of the coefficient set affect both the low pass and digital interpolation. In other cases, at least one of the two or more bits affect both the low pass and digital interpolation. As more fully described below, the coefficient set is generated based upon a combination of a phase offset value and a boost value.

Timing loop processing is applied to the filtered output to generate the aforementioned phase offset upon which the coefficient set is based (block 430). In some cases, such timing loop processing includes a first timing loop processing performed during an acquisition mode, and a second timing loop processing performed during a tracking mode. For both the timing loop processing performed during the tracking mode and the timing loop processing performed during the acquisition mode, a phase offset value is generated.

A look up value is determined based upon a combination of the phase offset value (generated in block 430) and the boost value (received in block 405)(block 435). The look up value may be generated by concatenating the boost value to the phase offset value. Alternatively, the look up value may be generated by applying a combining algorithm to a combination of the boost value and the phase offset value to yield a single value corresponding to the two inputs. Based upon the disclosure provided herein, one of ordinary skill in the art will recognize a variety of approaches that may be used to combine the boost value and the phase offset value into a single look up value.

Pre-programmed coefficient sets included in a look up table are accessed using the look up value (block 440). The coefficient set selected from the look up table using the look up value are provided to the circuit applying the combination of low pass and digital interpolation filtering. By using a coefficient set selected based upon a combination of the boost value and the phase offset value, a single simultaneous filtering process may be applied to yield both the desired low pass filtering and the phase rotation.

Turning to FIG. 5, a flow diagram 500 shows a method in accordance with some embodiments of the present invention for acquisition phase gain modification. Following flow diagram 500, data is received from a sensor or read head as the sensor flies over a track of a storage medium after being amplified by a preamplifier circuit (block 505). The received data is amplified by a gain feedback to yield an amplified output (block 510), and an analog to digital conversion is applied to the amplified output to yield a series of digital samples (i.e., ADC samples) (block 515). The resulting series of ADC samples are stored to a buffer (block 520). The buffer is a first in/first out buffer such that the samples are accessed from the buffer in the order in which they were received.

It is determined whether the data processing system is performing acquisition phase processing or tracking phase processing (block 525). In some embodiments, a signal is provided that indicates whether the data processing system is operating in the acquisition phase or the tracking phase. Where it is determined that the data processing system is not performing acquisition phase processing (block 525), then standard gain processing is performed (block 530). Such standard gain processing includes updating the gain feedback that controls the variable gain amplification of block 510 using any approach known in the art for modifying a gain feedback value during tracking phase processing.

Alternatively, where it is determined that the data processing system is performing acquisition phase processing (block 525), the amplitude of the ADC samples is estimated (block 535). This amplitude estimation may be done, for example, using a zero gain start (ZGS) circuit as are known in the art. Based upon the disclosure provided herein, one of ordinary skill in the art will recognize approaches and/or circuitry that may be used to estimate the amplitude of the ADC samples to yield an estimated amplitude.

It is determined whether the estimated amplitude is within a narrow window (block 540). This is determined by comparing the estimated amplitude with an upper threshold of the narrow window and a lower threshold of the narrow window. The upper threshold is an expected amplitude plus a narrow offset and the lower threshold is the expected amplitude minus the narrow offset. Where it is determined that the estimated amplitude is within the narrow window (block 540), the estimated amplitude is near the expected amplitude and the gain feedback is set equal to a default value (block 575). Said another way, the gain being applied by the variable gain amplification of block 510 is not changed.

Alternatively, where it is determined that the estimated amplitude is not within the narrow window (block 540), an overall gain offset is calculated (block 545). The overall gain offset is the magnitude and direction that the gain applied by variable gain amplification of block 510 would have to be adjusted to increase or decrease the ADC samples to match the expected amplitude. It is then determined whether the estimated amplitude is within a wide window (block 555). This is determined by comparing the estimated amplitude with an upper threshold of the wide window and a lower threshold of the wide window. The upper threshold is an expected amplitude plus a wide offset and the lower threshold is the expected amplitude minus the wide offset. Where it is determined that the estimated amplitude is within the wide window (block 555), the estimated amplitude is an intermediate distance from the expected amplitude. In such a case, the overall gain offset is applied to all buffered ADC samples to yield corrected samples (block 570). This is done by calculating a scalar value that corresponds to the overall gain offset. In particular, where the overall gain offset is positive indicating a need for increasing the gain applied by the variable gain amplification process, then the scalar is greater than unity by an amount corresponding to the magnitude of the overall gain offset. Otherwise, where the overall gain offset is negative indicating a need for decreasing the gain applied by the variable gain amplification process, then the scalar is less than unity by an amount corresponding to the magnitude of the overall gain offset. In addition, the gain feedback is set equal to a default value (block 575). Said another way, the gain being applied by the variable gain amplification of block 510 is not changed, but the ADC samples are scaled to reflect the overall gain offset.

Alternatively, where it is determined that the estimated amplitude is outside the wide window (block 555), the estimated amplitude is an extended distance from the expected amplitude. In such a case, the overall gain offset is divided by a number of bit periods over which the gain will be modified to achieve the overall gain. The number of bit periods are the number of periods (or less than the number of periods) remaining in the period over which the acquisition phase processing is performed. In some embodiments, this number of periods is fixed, while in other embodiments this number of periods is user programmable.

The period gain is incrementally applied to all buffered ADC samples to yield corrected samples (block 560). This incremental application includes setting a scalar by which the ADC samples will be multiplied equal to the period gain for a first bit period, and increasing the scalar by the period gain for each subsequent bit period. Thus, during the second bit period the scalar is set to two times the period gain, during the third bit period the scalar is set to three times the period gain, and so on. In addition, the gain feedback used to control the variable gain multiplication is incrementally adjusted to reflect the period gain (block 565). This incremental adjustment of the gain feedback includes modifying the gain feedback to introduce a change corresponding to the period gain for a first bit period, and increasing (or decreasing) the gain feedback by an amount corresponding to the period gain for each subsequent bit period. Thus, during the second bit period the gain feedback is modified to reflect two times the period gain, during the third bit period the gain feedback is modified to reflect three times the period gain, and so on.

Turning to FIG. 6, a block diagram of another data processing circuit 600 including an integrated low pass and rotation filtering circuit 619 in accordance with various embodiments of the present invention. Data processing circuit 600 includes an analog processing circuit 604 receives data 302 from a read head included as part of a read/write head (not shown). Data 602 is received as an analog signal derived from sensing information from a track on the storage medium (not shown). Analog processing circuit 604 may include a variety of analog processing circuitry including, but not limited to, a preamplifier circuit, an analog filter circuit, a variable gain amplifier circuit, a DC offset circuit, and/or a magneto resistive asymmetry (MRA) modification circuit. Based upon the disclosure provided herein, one of ordinary skill in the art will recognize a variety of circuitry that may be included as part of analog processing circuit 604. Analog processing circuit 604 applies the aforementioned analog processing to yield a processed analog output 606.

Processed analog output 606 is provided to an analog to digital converter circuit 608 where it is converted into a series of digital samples 610. Digital samples 610 are provided both to a phase modification determination circuit 624 and integrated low pass and rotation filtering circuit 619. Integrated low pass and rotation filtering circuit 619 simultaneously applies a low pass filtering function and a phase rotation function to digital samples 610 to yield modified samples 618. Phase modification determination circuit 624 determines a phase error based upon either digital samples 610 or modified samples 618. The determined phase error is provided as a phase offset value 625 to integrated low pass and rotation filtering circuit 619. In some cases, phase modification determination circuit 624 includes a first circuit operable to determine phase offset value 625 during an acquisition phase, and a second circuit operable to determine phase offset value 625 during a tracking phase.

Integrated low pass and rotation filtering circuit 619 includes a boost and phase adjustment selection circuit 611, a look up table 615, and an integrated digital low pass and interpolation filter circuit 616. In operation, integrated digital low pass and interpolation filter circuit 616 simultaneously applies both a low pass filtering function and a phase rotation function to digital samples 610 to yield modified samples 618 based upon a coefficient set 617 from look up table 615. In some cases, coefficient set 617 includes two or more bits where at least one of the two or more bits when modified impacts both the low pass filtering function and the phase rotation function. In other cases, coefficient set 617 includes two or more bits where all of the two or more bits when modified each impact both the low pass filtering function and the phase rotation function. As more fully described below, coefficient set 617 is generated based upon a combination of phase offset value 625 and a user programmable filter boost value 603.

Boost and phase selection circuit 611 receives phase offset value 625 and user programmable filter boost value 603. In some embodiments of the present invention, boost and phase selection circuit 611 determines look up value 613 by concatenating boost value 603 to the phase offset value 625. Alternatively, boost and phase selection circuit 611 determines look up value 613 by applying a combining algorithm to a combination of boost value 603 and phase offset value 625. Based upon the disclosure provided herein, one of ordinary skill in the art will recognize a variety of approaches that may be used to combine the boost value and the phase offset value into a single look up value.

Look up value 613 is provided to look up table 615 that is pre-programmed with a number of coefficient sets each corresponding to different combinations of phase offset and boost to be implemented by integrated digital low pass and interpolation filter circuit 616. In response to receiving look up value 613, look up table 615 provides the corresponding pre-programmed coefficient set as coefficient set 617 to integrated digital low pass and interpolation filter circuit 616.

It should be noted that while the circuits and methods are discussed in relation to processing data from a single read head on a read/write head, other embodiments of the present invention apply the circuits and/or methods to processing data from multiple read heads an a read/write head. In such embodiments, the various elements are replicated for use in relation to each of the multiple read heads individually.

Additionally, it should be noted that the various blocks discussed in the above application may be implemented in integrated circuits along with other functionality. Such integrated circuits may include all of the functions of a given block, system or circuit, or a subset of the block, system or circuit. Further, elements of the blocks, systems or circuits may be implemented across multiple integrated circuits. Such integrated circuits may be any type of integrated circuit known in the art including, but are not limited to, a monolithic integrated circuit, a flip chip integrated circuit, a multichip module integrated circuit, and/or a mixed signal integrated circuit. It should also be noted that various functions of the blocks, systems or circuits discussed herein may be implemented in either software or firmware. In some such cases, the entire system, block or circuit may be implemented using its software or firmware equivalent, albeit such a system would not be a circuit. In other cases, the one part of a given system, block or circuit may be implemented in software or firmware, while other parts are implemented in hardware.

In conclusion, the invention provides novel systems, devices, methods and arrangements for data processing. While detailed descriptions of one or more embodiments of the invention have been given above, various alternatives, modifications, and equivalents will be apparent to those skilled in the art without varying from the spirit of the invention. Therefore, the above description should not be taken as limiting the scope of the invention, which is defined by the appended claims. 

1. A data processing system, the system comprising: a phase modification value determination circuit operable to generate a phase offset value based upon an input data set derived from information sensed from a storage medium; an integrated low pass and rotation filtering circuit operable to simultaneously apply a low pass filtering function and phase rotation function to a series of digital samples derived from the information sensed from the storage medium to yield a modified output, wherein application of both the low pass filtering and phase rotation functions is governed at least in part based upon a selected coefficient set corresponding to a combination of the phase off set value and a boost value.
 2. The system of claim 1, wherein the boost value is user programmable.
 3. The system of claim 1, wherein the low pass and rotation filtering circuit comprises: a look up table operable to maintain a plurality of coefficient sets including the selected coefficient set; and an integrated low pass and interpolation filter circuit operable to simultaneously apply the low pass filtering and phase rotation functions to the series of digital samples.
 4. The system of claim 3, wherein the low pass and rotation filtering circuit further comprises: a boost and phase adjustment selection circuit operable to determine a look up value corresponding to the selected coefficient set based upon the combination of the phase off set value and the boost value.
 5. The system of claim 1, wherein the coefficient set includes at least two bits, and wherein at least one of the at least two bits when modified impacts both the low pass filtering function and the phase rotation function.
 6. The system of claim 1, wherein the coefficient set includes at least two bits, and wherein all of the at least two bits when modified each impact both the low pass filtering function and the phase rotation function.
 7. The system of claim 1, wherein the phase modification value determination circuit includes a first circuit and a second circuit, and wherein: the first circuit is operable to generate a first value during an acquisition mode; and the second circuit is operable to generate a second value during a tracking mode; and wherein the first value is selected as the phase offset value during the acquisition mode, and the second value is selected as the phase offset value during the tracking mode.
 8. The system of claim 1, wherein the system is implemented as part of a storage device including: the storage medium; a head disposed in relation to the storage medium, and operable to sense the information from the storage medium; and an analog to digital converter circuit operable to convert an input derived from the information set into the series of digital samples.
 9. The system of claim 8, the system further comprising: an equalizer circuit operable to equalize the modified output to yield an equalized output; a data detector circuit operating on the equalized output to yield a detected output; and a timing update loop circuit operable to generate the phase offset value.
 10. The data processing system of claim 1, wherein the system is implemented as part of an integrated circuit.
 11. A method for integrated filtering and phase rotation, the method comprising: receiving a series of digital samples; determining a phase offset value based upon the series of digital samples; and using an integrated low pass and rotation filtering circuit to simultaneously apply a low pass filtering function and phase rotation function to the series of digital samples to yield a modified output, wherein application of both the low pass filtering and phase rotation functions is governed at least in part based upon a selected coefficient set corresponding to a combination of the phase offset value and a boost value.
 12. The method of claim 1, wherein applying the low pass function and rotation filtering function comprises: accessing a look up table programmed to include a plurality of coefficient sets, wherein the selected coefficient set is one of the plurality of coefficient sets.
 13. The method of claim 12, wherein applying the low pass function and rotation filtering function comprises: determining a look up value corresponding to the selected coefficient set based upon the combination of the phase off set value and the boost value.
 14. The method of claim 13, wherein determining the look up value includes concatenating the boost value and the phase offset value.
 15. The method of claim 11, wherein the boost value is user programmable.
 16. The method of claim 11, wherein the coefficient set includes at least two bits, and wherein at least one of the at least two bits when modified impacts both the low pass filtering function and the phase rotation function.
 17. The method of claim 11, wherein the coefficient set includes at least two bits, and wherein all of the at least two bits when modified each impact both the low pass filtering function and the phase rotation function.
 18. The method of claim 11, wherein determining the phase off set value using a first circuit to generate a first value during an acquisition mode; using a second circuit to generate a second value during an acquisition mode; and selecting the first value as the phase offset value during the acquisition mode, and selecting the second value as the phase off set value during the tracking mode.
 19. A storage device, the storage device comprising: a head including a read sensor disposable over a storage medium and operable to sense information on the storage medium and provide a corresponding sensed signal; a variable gain amplifier circuit operable to amplify an input signal derived from the sensed signal by a variable gain corresponding to a gain feedback value to yield an amplified output; an analog to digital converter circuit operable to convert an analog input into a series of digital samples, wherein the series of digital samples includes a preamble pattern, and wherein the analog input is derived from the amplified output; a phase modification value determination circuit operable to generate a phase offset value based upon an input data set derived from the series of digital samples; and an integrated low pass and rotation filtering circuit operable to simultaneously apply a low pass filtering function and phase rotation function to a series of digital samples derived from the information sensed from the storage medium to yield a modified output, wherein application of both the low pass filtering and phase rotation functions is governed at least in part based upon a selected coefficient set corresponding to a combination of the phase offset value and a boost value.
 20. The storage device of claim 19, wherein the low pass and rotation filtering circuit comprises: a look up table operable to maintain a plurality of coefficient sets including the selected coefficient set; an integrated low pass and interpolation filter circuit operable to simultaneously apply the low pass filtering and phase rotation functions to the series of digital samples; and a boost and phase adjustment selection circuit operable to determine a look up value corresponding to the selected coefficient set based upon the combination of the phase offset value and the boost value. 